The present invention relates generally to the testing of semiconductor devices and, more particularly, to the testing of semiconductor devices via a back side involving laser-induced circuit excitation.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or xe2x80x9cflip-chipxe2x80x9d packaging. This packaging technology involves providing bonding pads of the die with metal (solder) bumps. Electrical connection to the package is made when the die is xe2x80x9cflippedxe2x80x9d over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances the orientation of the die with the circuit side face down on a substrate is disadvantageous. Due to this face down orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification, or other purposes. Consequently, access to the transistors and circuitry near the circuit side must be from the back side of the chip, and testing methods are limited to those that are feasible using back side access. In addition to flip-chip type devices, back side access is also sometimes necessary or beneficial for other semiconductor devices.
A particular attribute of semiconductor manufacturing involves testing the integrity of device circuitry, such as metal interconnects, transistors, and other devices found in integrated circuits. Ensuring the integrity of such devices is important for maintaining proper circuit function, reliability, and longevity. Therefore, the semiconductor industry would benefit from practical methods for analyzing semiconductor devices that require back side access to circuitry within such devices. In addition, the semiconductor industry would further benefit from practical methods for analyzing semiconductor devices during their manufacture. Testing devices during their manufacture, among other things, would provide an opportunity to test the device non-destructively without the need for accessing through substrate in the back side of the device.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for testing active circuitry in a semiconductor device having a circuit side and an opposing back side. A laser is directed at the device via the back side and circuitry in the circuit side is selectively excited. In response to exciting circuitry, target circuitry is monitored and a degree of integrity of the operation of the semiconductor device is determined. This embodiment provides, among other things, an innovative method for testing semiconductor devices requiring or benefiting from back side testing.
According to another example embodiment, the present invention includes an apparatus for testing a semiconductor device having a circuit side, an opposing back side, active circuitry, and an active device coupled via circuitry to output pins. The system comprises an ion bombardment device for removing substrate from the back side of the device. A power supply is used for powering the device at a stress power level, and a laser device is used for exciting the active circuitry. Monitors are used to monitor target circuitry coupled to the active circuitry and to monitor passive emissions of the active device. The monitored target circuitry and passive emissions are used by a processor to determine a degree of integrity of the operation of the semiconductor device.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.